Integrated circuit memory devices may be used in electronic devices to store data. Furthermore, integrated circuit memory devices that consume a relatively small amount of power may be used in electronic devices that use power supplied from, for example, a battery. Manufacturers of integrated circuit devices have tried to reduce the overall power consumption of integrated circuit memory devices by, for example, changing a structure of a driver used to drive input/output (I/O) lines of the integrated circuit device during a write operation. A driver may be, for example, a pull-up transistor. Conventionally, positive-channel metal oxide semiconductor (PMOS) transistors have been used as the pull-up transistors. However, recently, the PMOS transistors have been replaced with negative channel metal oxide semiconductor (NMOS) transistors as NMOS transistors may consume less power.
In particular, when PMOS transistors are used as the pull-up transistor in a driver of an integrated circuit device, an I/O line may swing from a ground voltage (GND) to a power supply voltage (VCC) or vice versa. On the other hand, when an NMOS transistor is used as the pull-up transistor in a driver of an integrated circuit memory device, an I/O line may only swing from the ground voltage to a power supply voltage (VCC) decreased by a threshold voltage of the NMOS transistor (Vth) or vice versa. Accordingly, it may be possible to reduce current consumed when the I/O line is driven.
Referring now to FIG. 1, an I/O line driver circuit using an NMOS transistor as a pull-up transistor will be discussed. As illustrated in FIG. 1, an I/O line driver circuit 10 includes first and second drivers DRV1 and DRV2 that drive a pair of differential I/O lines IO<0> and IOB<0>, respectively. The first and second drivers DRV1 and DRV2 are pull-up transistors. The first driver DRV1 includes first and second NMOS transistors M1 and M2. Similarly, the second driver DRV2 includes third and fourth NMOS transistors M3 and M4. A precharge circuit 20 is coupled to the pair of differential I/O lines IO<0> and IOB<0> and includes first, second, and third PMOS transistors M5, M6, and M7. When the precharge circuit 20 is activated, the pair of differential I/O lines IO<0> and IOB<0> are precharged to a power supply voltage VCC.
It will be understood that although only a single I/O line driver circuit corresponding to a single pair of differential I/O lines and a single precharge circuit are shown in FIG. 1, I/O lines corresponding to the other pairs of differential I/O lines and other precharge circuits may be included. A plurality of pairs of differential I/O lines may be connected to a memory bank having a plurality of memory blocks. A single memory bank is illustrated in FIG. 1.
Referring now to the schematic block diagram of FIG. 1 and the timing diagrams of FIGS. 2 through 4, an active command signal PWR may be activated to store external data in a memory bank and a write command signal CBA_A may be activated responsive to the activation of the active command PWR. When the write command signal CBA_A is activated, an I/O line precharge signal PIOPRB_A is deactivated (to a logic high) and a write pulse signal PDT_A is activated.
Prior to the activation of the write command signal CBA_A, first, second and third PMOS transistors M5, M6, and M7 of precharge circuit 20 are turned on to precharge the pair of differential I/O lines IO<0> and IOB<0> to a power supply voltage VCC. Because, at this time, the write pulse signal PDT_A is deactivated at a logic low (FIG. 2), first, second, third and fourth NMOS transistors M1 through M4 are all turned off.
When the write command signal CBA_A is activated, first through third PMOS transistors M5 through M7 of the precharge circuit 20 are turned off and the first through fourth NMOS transistors M1 through M4 are selectively turned on according to input data DIO<0>. For example, when the input data DIO<0> is “1”, the first and fourth NMOS transistors M1 and M4 are turned off and the second and third NMOS transistors M2 and M3 are turned on. When all the input data DIO<0> is written to a selected memory bank, the write command signal CBA_A may be deactivated and the pair of differential I/O lines IO<0> and IOB<0> may again be precharged to the power supply voltage VCC.
A data masking signal PDMB may be activated (to a logic low) during a write operation. With the activation of the data masking signal PDMB, pairs of differential I/O lines of respective memory banks may be precharged and the first through fourth NMOS transistors M1 through M4 may all be turned off.
Although the use of NMOS transistors as pull-up transistors in place of PMOS transistors has reduced power consumption of integrated circuit memory devices, integrated circuit devices including the NMOS transistors may experience decreased performance in other aspects of the device, which will now be discussed with respect to the timing diagrams of FIGS. 2 through 4. When input data DIO<0> is first loaded on the pair of differential I/O lines, there is typically a skew, i.e., difference in arrival time of the input data, between ones of the pair of differential I/O lines. Because the I/O lines are precharged to a power supply voltage VCC, the first driver DRV1 or the second driver DRV2 of an I/O line driver circuit 10 cannot drive an I/O line having a voltage of VCC−Vth. For example, when input data DIO<0> is “1”, second and third NMOS transistors M2 and M3 of the driver circuit 10 are turned on. On the other hand, because gate and source voltages of the third NMOS transistor M3 are all at the power supply voltage VCC, the NMOS transistor M3 is turned off. Thus, a voltage, for example, a precharge voltage VCC, of the I/O line IOB<0> is maintained. When input data DIO<0> is “0”, the first and fourth NMOS transistors M1 and M4 of the driver circuit 10 are turned on. This enables the first NMOS transistor M1 to drive the I/O line IOB<0> with VCC−Vth and enables the fourth NMOS transistor M4 to discharge a voltage, for example, a precharge voltage VCC, of the I/O line IO<0> to a ground voltage (GND).
As illustrated by dotted lines of FIGS. 2 through 4, when data is loaded on the pair of differential I/O lines, there may be a skew between the I/O lines IO<0> and IOB<0>. This skew typically occurs whenever I/O lines are precharged and data is loaded on the precharged I/O lines. Accordingly, during a seamless write operation where data is successively stored in successive memory banks, I/O lines of a previously selected memory bank are precharged after the write operation is complete for that memory bank. For example, I/O lines of a first bank A may be precharged after a write operation is completed, as shown in FIG. 4. After a write operation for the second bank B a write operation for the first bank A is conducted. At this time, the I/O lines of the second bank B are precharged to VCC. Thus, when the seamless write operation is conducted, I/O lines of an unselected memory bank or previously selected memory bank may be unnecessarily precharged.